ARM DEN0013C - Appendix A Instruction Summary

ARM認定エンジニア認定資格の試験を 1/30(木)に受験する予定で、ARMのアセンブラを弄って勉強しています。しかし、このまま思いつくままのやり方では試験要綱へのカバー範囲が偏るのが心配(汗)　。。。ということで、

Cortex-A Series
Version: 3.0
Programmer’s Guide
ARM DEN0013C (ID071612)

の

Appendix A Instruction Summary

を一覧表にまとめてみました。
Perlでスクリプトを作って抜き出したので写し間違いは無いと思いますが、内容の正確さとか有用性は保証はできませんm(_ _)m

ブログのページ幅の関係で美しくないですが、コピペして Microsoft Excel や Libre Office Calc に張り付けるとちゃんとスプレッドシートになります。

A.1.1	ADC	Add with Carry	ADC{S}{cond} {Rd}, Rn, <Operand2>
A.1.2	ADD	ADD adds together the values in Rn and Operand2 (or Rn and imm12).	ADD{S}{cond} {Rd,} Rn, <Operand2>
A.1.3	ADR	Address	ADR{cond} Rd, label
A.1.4	ADRL	Address	ADRL{cond} Rd, label
A.1.5	AND	AND does a bitwise AND on the values in Rn and Operand2.	AND{S}{cond} {Rd,} Rn, <Operand2>
A.1.6	ASR	Arithmetic Shift Right	ASR{S}{cond} {Rd,} Rm, Rs ASR{S}{cond} {Rd,} Rm, imm
A.1.7	B	Branch	B{cond}{.W} label
A.1.8	BFC	Bit Field Clear	BFC{cond} Rd, #lsb, #width
A.1.9	BFI	Bit Field Insert	BFI{cond} Rd, Rn, #lsb, #width
A.1.10	BIC	bit clear	BIC{S}{cond} {Rd}, Rn, <Operand2>
A.1.11	BKPT	Breakpoint	BKPT #imm
A.1.12	BL	Branch with Link	BL{cond} label
A.1.13	BLX	Branch with Link and eXchange	BLX{cond} label BLX{cond} Rm
A.1.14	BX	Branch and eXchange	BX{cond} Rm
A.1.15	BXJ	Branch and eXchange Jazelle	BXJ{cond} Rm
A.1.16	CBNZ	Compare and Branch if Nonzero	CBNZ Rn, label
A.1.17	CBZ	Compare and Branch if Zero	CBZ Rn, label
A.1.18	CDP	Coprocessor Data Processing operation	CDP{cond} coproc, #opcode1, CRd, CRn, CRm{, #opcode2}
A.1.19	CDP2	Coprocessor Data Processing operation	CDP2{cond} coproc, #opcode1, CRd, CRn, CRm{, #opcode2}
A.1.20	CHKA	Check array	CHKA Rn, Rm
A.1.21	CLREX	Clear Exclusive	CLREX{cond}
A.1.22	CLZ	Count Leading Zeros	CLZ{cond} Rd, Rm
A.1.23	CMN	Compare Negative	CMN{cond} Rn, <Operand2>
A.1.24	CMP	Compare	CMP{cond} Rn, <Operand2>
A.1.25	CPS	Change Processor State	CPS #mode CPSIE iflags{, #mode} CPSID iflags{, #mode}
A.1.26	DBG	Debug	DBG{cond} {option}
A.1.27	DMB	Data Memory Barrier	DMB{cond} {option}
A.1.28	DSB	Data Synchronization Barrier	DSB{cond} {option}
A.1.29	ENTERX	ENTERX causes a change from Thumb state to ThumbEE state, or has no effect in ThumbEE state.	ENTERX
A.1.30	EOR	EOR performs an Exclusive OR operation on the values in Rn and Operand2.	EOR{S}{cond} {Rd,} Rn, <Operand2>
A.1.31	ERET	Exception Return	ERET{cond} {q}
A.1.32	HB	Handler Branch	HB{L} #HandlerID HB{L}P #imm, #HandlerID
A.1.33	ISB	Instruction Synchronization Barrier	ISB{cond} {option}
A.1.34	IT	If-then	IT{x{y{z}}} {cond}
A.1.35	LDC	Load Coprocessor Registers	LDC{L}{cond} coproc, CRd, [Rn] LDC{L}{cond} coproc, CRd, [Rn, #{-}offset]{!} LDC{L}{cond} coproc, CRd, [Rn], #{-}offset LDC{L}{cond} coproc, CRd, label
A.1.36	LDC2	Load Coprocessor Registers	LDC2{L}{cond} coproc, CRd, [Rn] LDC2{L}{cond} coproc, CRd, [Rn, #{-}offset]{!} LDC2{L}{cond} coproc, CRd, [Rn], #{-}offset LDC2{L}{cond} coproc, CRd, label
A.1.37	LDM	Load Multiple registers	LDM{addr_mode}{cond} Rn{!},reglist{^}
A.1.38	LDR	Load Register	LDR{type}{T}{cond} Rt, [Rn {, #offset}] LDR{type}{cond} Rt, [Rn, #offset]! LDR{type}{T}{cond} Rt, [Rn], #offset LDR{type}{cond} Rt, [Rn, +/-Rm {, shift}] LDR{type}{cond} Rt, [Rn, +/-Rm {, shift}]! LDR{type}{T}{cond} Rt, [Rn], +/-Rm {, shift}
A.1.39	LDR	Load Register	LDR{cond}{.W} Rt, =expr LDR{cond}{.W} Rt, label_expr
A.1.40	LDRD	Load Register Dual	LDRD{cond} Rt, Rt2, [{Rn},+/-{Rm}]{!} LDRD{cond} Rt, Rt2, [{Rn}],+/-{Rm}
A.1.41	LDREX	Load register exclusive	LDREX{cond} Rt, [Rn {, #offset}] LDREXB{cond} Rt, [Rn] LDREXH{cond} Rt, [Rn] LDREXD{cond} Rt, Rt2, [Rn]
A.1.42	LEAVEX	LEAVEX causes a change from ThumbEE state to Thumb state, or has no effect in Thumb state.	LEAVEX
A.1.43	LSL	Logical Shift Left	LSL{S}{cond} Rd, Rm, Rs LSL{S}{cond} Rd, Rm, imm
A.1.44	LSR	Logical Shift Right	LSR{S}{cond} Rd, Rm, Rs LSR{S}{cond} Rd, Rm, imm
A.1.45	MCR	Move to Coprocessor from Register	MCR{cond} coproc, #opcode1, Rt, CRn, CRm{, #opcode2}
A.1.46	MCR2	Move to Coprocessor from Register	MCR2{cond} coproc, #opcode1, Rt, CRn, CRm{, #opcode2}
A.1.47	MCRR	Move to Coprocessor from Registers	MCRR{cond} coproc, #opcode3, Rt, Rt2, CRm
A.1.48	MCRR2	Move to Coprocessor from Registers	MCRR2{cond} coproc, #opcode3, Rt, Rt2, CRm
A.1.49	MLA	Multiply Accumulate	MLA{S}{cond} Rd, Rn, Rm, Ra
A.1.50	MLS	Multiply and Subtract	MLS{S}{cond} Rd, Rn, Rm, Ra
A.1.51	MOV	Move	MOV{S}{cond} Rn, <Operand2> MOV{cond} Rd, #imm16
A.1.52	MOVT	Move Top	MOVT{cond} Rd, #imm16
A.1.53	MOV32	MOV32 is a pseudo-instruction which loads a register with a 32-bit immediate value or address.	MOV32 Rd, expr
A.1.54	MRC	Move to Register from Coprocessor	MRC{cond} coproc, #opcode1, Rt, CRn, CRm{, #opcode2}
A.1.55	MRC2	Move to Register from Coprocessor	MRC2{cond} coproc, #opcode1, Rt, CRn, CRm{, #opcode2}
A.1.56	MRRC	Move to Registers from Coprocessor	MRRC{cond} coproc, #opcode3, Rt, Rt2, CRm
A.1.57	MRRC2	Move to Registers from Coprocessor	MRRC2{cond} coproc, #opcode3, Rt, Rt2, CRm
A.1.58	MRS	Move Status register or Coprocessor Register to General purpose register	MRS{cond} Rd, psr MRS{cond} Rn, coproc_register MRS{cond} APSR_nzcv, DBGDSCRint MRS{cond} APSR_nzcv, FPSCR
A.1.59	MSR	Move Status Register or Coprocessor Register from General Purpose Register	MSR{cond} APSR_flags, Rm MSR{cond} coproc_register MSR{cond} APSR_flags, #constant MSR{cond} psr_fields, #constant MSR{cond} psr_fields, Rm
A.1.60	MUL	Multiply	MUL{S}{cond} {Rd,} Rn, Rm
A.1.61	MVN	Move Not	MVN{S}{cond} Rn, <Operand2>
A.1.62	NOP	No Operation	NOP{cond}
A.1.63	ORN	OR NOT	ORN{S}{cond} {Rd,} Rn, <Operand2>
A.1.64	ORR	Performs an OR operation on the bits in Rn with the corresponding bits in the value of Operand2.	ORR{S}{cond} {Rd,} Rn, <Operand2>
A.1.65	PKHBT	Pack Halfword Bottom Top	PKHBT{cond} {Rd,} Rn, Rm{, LSL #leftshift}
A.1.66	PKHTB	Pack Halfword Top Bottom	PKHTB{cond} {Rd,} Rn, Rm {, ASR #rightshift}
A.1.67	PLD	Preload Data	PLD{cond} [Rn {, #offset}] PLD{cond} [Rn, +/-Rm {, shift}] PLD{cond} label
A.1.68	PLDW	Preload data with intent to write	PLDW{cond} [Rn {, #offset}] PLDW{cond} [Rn, +/-Rm {, shift}]
A.1.69	PLI	Preload instructions	PLI{cond} [Rn {, #offset}] PLI{cond} [Rn, +/-Rm {, shift}] PLI{cond} label
A.1.70	POP	POP is used to pop registers off a full descending stack.	POP{cond} reglist
A.1.71	PUSH	PUSH is used to push registers on to a full descending stack.	PUSH{cond} reglist
A.1.72	QADD	Saturating signed Add	QADD{cond} {Rd,} Rm, Rn
A.1.73	QADD8	Saturating signed bytewise Add	QADD8{cond} {Rd,} Rn, Rm
A.1.74	QADD16	Saturating signed bytewise Add	QADD16{cond} {Rd,} Rn, Rm
A.1.75	QASX	Saturating signed Add Subtract eXchange	QASX{cond} {Rd,} Rn, Rm
A.1.76	QDADD	Saturating signed Add	QDADD{cond} {Rd,} Rm, Rn
A.1.77	QDSUB	Saturating signed Doubling Subtraction	QDSUB{cond} {Rd,} Rm, Rn
A.1.78	QSAX	Saturating signed Subtract Add Exchange	QSAX{cond} {Rd,} Rn, Rm
A.1.79	QSUB	Saturating signed Subtraction	QSUB{cond} {Rd,} Rm, Rn
A.1.80	QSUB8	Saturating signed bytewise Subtract	QSUB8{cond} {Rd,} Rn, Rm
A.1.81	QSUB16	Saturating signed halfword Subtract	QSUB16{cond} {Rd,} Rn, Rm
A.1.82	RBIT	Reverse bits	RBIT{cond} Rd, Rn
A.1.83	REV	Reverse	REV{cond} {Rd}, Rn
A.1.84	REV16	Reverse byte order halfwords	REV16{cond} {Rd}, Rn
A.1.85	REVSH	Reverse byte order halfword, with sign extension	REVSH{cond} Rd, Rn
A.1.86	RFE	Return from Exception	RFE{addr_mode}{cond} Rn{!}
A.1.87	ROR	Rotate right Register	ROR{S}{cond} {Rd,} Rm, Rs ROR{S}{cond} {Rd,} Rm, imm
A.1.88	RRX	Rotate Right with extend	RRX{S}{cond} {Rd,} Rm
A.1.89	RSB	Reverse Subtract	RSB{S}{cond} {Rd,} Rn, <Operand2>
A.1.90	RSC	Reverse Subtract with Carry	RSC{S}{cond} {Rd,} Rn, <Operand2>
A.1.91	SADD8	Signed bytewise Add	SADD8{cond} {Rd,} Rn, Rm
A.1.92	SADD16	Signed bytewise Add	SADD16{cond} {Rd,} Rn, Rm
A.1.93	SASX	Signed Add Subtract Exchange	SASX{cond} {Rd,} Rn, Rm
A.1.94	SBC	Subtract with Carry	SBC{S}{cond} {Rd,} Rn, <Operand2>
A.1.95	SBFX	Signed Bit Field Extract	SBFX{cond} Rd, Rn, #lsb, #width
A.1.96	SDIV	Signed Divide	SDIV{cond}{q} {Rd,} Rn, Rm
A.1.97	SEL	Select	SEL{cond} {Rd,} Rn, Rm
A.1.98	SETEND	Set endianness	SETEND LE SETEND BE
A.1.99	SEV	Send Event	SEV{cond}
A.1.100	SHADD8	Signed halving bytewise Add	SHADD8{cond} {Rd,} Rn, Rm
A.1.101	SHADD16	Signed halving bytewise Add	SHADD16{cond} {Rd,} Rn, Rm
A.1.102	SHASX	Signed Halving Add Subtract Exchange	SHASX{cond} {Rd,} Rn, Rm
A.1.103	SHSAX	Signed Halving Subtract Add Exchange	SHSAX{cond} {Rd,} Rn, Rm
A.1.104	SHSUB8	Signed halving bytewise subtraction	SHSUB8{cond} {Rd,} Rn, Rm
A.1.105	SHSUB16	Signed Halving halfword-wise Subtract	SHSUB16{cond} {Rd,} Rn, Rm
A.1.106	SMC	Secure Monitor Call	SMC{cond} #imm4
A.1.107	SMLAxy	Signed Multiply Accumulate; 32 <= 32 + 16 * 16	SMLA<x><y>{cond} Rd, Rn, Rm, Ra
A.1.108	SMLAD	Dual Signed Multiply Accumulate; 32 <= 32 + 16 * 16 + 16 * 16	SMLAD{X}{cond} Rd, Rn, Rm, Ra
A.1.109	SMLAL	Signed Multiply Accumulate 64 <= 64 + 32 * 32	SMLAL{S}{cond} RdLo, RdHi, Rn, Rm
A.1.110	SMLALxy	Signed Multiply Accumulate; 64 <= 64 + 16 * 16	SMLAL<x><y>{cond} RdLo, RdHi, Rn, Rm
A.1.111	SMLALD	Dual Signed Multiply Accumulate Long; 64 <= 64 + 16 * 16 + 16 * 16	SMLALD{X}{cond} RdLo, RdHi Rn, Rm
A.1.112	SMLAWy	Signed Multiply with Accumulate Wide; 32 <= 32 * 16 + 32	SMLAW<y>{cond} Rd, Rn, Rm, Ra
A.1.113	SMLSLD	Dual Signed Multiply Subtract Accumulate Long; 64 <= 64 + 16 * 16 - 16 * 16	SMLSLD{X}{cond} RdLo, RdHi Rn, Rm
A.1.114	SMMLA	Signed top word Multiply with Accumulate; 32 <= top word	SMMLA{R}{cond} Rd, Rn, Rm, Ra
A.1.115	SMMLS	Signed top word Multiply with Subtract; 32 <= top word	SMMLS{R}{cond} Rd, Rn, Rm, Ra
A.1.116	SMMUL	Signed top word Multiply; 32 <= top word	SMMUL{R}{cond} Rd, Rn, Rm
A.1.117	SMUAD	Dual Signed Multiply and Add products	SMUAD{X}{cond} Rd, Rn, Rm
A.1.118	SMUSD	Dual Signed Multiply and Subtract products	SMUSD{X}{cond} Rd, Rn, Rm
A.1.119	SMULxy	Signed Multiply; 32 <= 16 * 16	SMUL<x><y>{cond} {Rd}, Rn, Rm
A.1.120	SMULL	signed multiply long; 64 <= 32 * 32	SMULL{S}{cond} RdLo, RdHi, Rn, Rm
A.1.121	SMULWy	Signed Multiply Wide; 32 <= 32 * 16	SMULW<y>{cond} {Rd}, Rn, Rm
A.1.122	SRS	Store Return State	SRS{addr_mode}{cond} sp{!}, #modenum
A.1.123	SSAT	Signed Saturate	SSAT{cond} Rd, #sat, Rm{, shift}
A.1.124	SSAT16	Signed Saturate, parallel halfwords	SSAT16{cond} Rd, #sat, Rn
A.1.125	SSAX	Signed Subtract Add Exchange	SSAX{cond} {Rd,} Rn, Rm
A.1.126	SSUB8	Signed halving bytewise Subtraction	SSUB8{cond} {Rd,} Rn, Rm
A.1.127	SSUB16	Signed halfword-wise Subtract	SSUB16{cond} {Rd}, Rn, Rm
A.1.128	STC	Store Coprocessor Registers	STC{L}{cond} coproc, CRd, [Rn] STC{L}{cond} coproc, CRd, [Rn, #{-}offset]{!} STC{L}{cond} coproc, CRd, [Rn], #{-}offset STC{L}{cond} coproc, CRd, label
A.1.129	STC2	Store Coprocessor registers	STC2{L}{cond} coproc, CRd, [Rn] STC2{L}{cond} coproc, CRd, [Rn, #{-}offset]{!} STC2{L}{cond} coproc, CRd, [Rn], #{-}offset STC2{L}{cond} coproc, CRd, label
A.1.130	STM	Store Multiple registers	STM{addr_mode}{cond} Rn{!},reglist{^}
A.1.131	STR	Store Register	STR{type}{T}{cond} Rt, [Rn {, #offset}] STR{type}{cond} Rt, [Rn, #offset]! STR{type}{T}{cond} Rt, [Rn], #offset STR{type}{cond} Rt, [Rn, +/-Rm {, shift}] STR{type}{cond} Rt, [Rn, +/-Rm {, shift}]! STR{type}{T}{cond} Rt, [Rn], +/-Rm {, shift}
A.1.132	STRD	Store Register Dual	STRD{cond} Rt, Rt2, [Rn {,#+/-<imm>}] STRD{cond} Rt, Rt2, [<Rn>, #+/-<imm> STRD{cond} Rt, Rt2, [<Rn>, #+/-<imm>]! STRD{cond} Rt, Rt2, [{Rn},+/-{Rm}]{!} STRD{cond} Rt, Rt2, [{Rn}],+/-{Rm}
A.1.133	STREX	Store register exclusive	STREX{cond} Rd, Rt, [Rn {, #offset}] STREXB{cond} Rd, Rt, [Rn] STREXH{cond} Rd, Rt, [Rn] STREXD{cond} Rd, Rt, Rt2, [Rn]
A.1.134	SUB	Subtract	SUB{S}{cond} {Rd,} Rn, <Operand2>
A.1.135	SVC	SuperVisor Call	SVC{cond} #imm
A.1.136	SWP	Swap registers and memory	SWP{B}{cond} Rt, Rt2, [Rn]
A.1.137	SXT	Signed Extend	SXT<extend>{cond} {Rd,} Rm {,rotation}
A.1.138	SXTA	Signed Extend and Add	SXTA<extend>{cond} {Rd,} Rn, Rm {,rotation}
A.1.139	SYS	System coprocessor instruction	SYS{cond} instruction {,Rn}
A.1.140	TBB	Table Branch Byte	TBB [Rn, Rm]
A.1.141	TBH	Table Branch Halfword	TBH [Rn, Rm, LSL #1]
A.1.142	TEQ	Test Equivalence	TEQ{cond} Rn, <Operand2>
A.1.143	TST	Test	TST{cond} Rn, <Operand2>
A.1.144	UADD8	Unsigned bytewise Add	UADD8{cond} {Rd,} Rn, Rm
A.1.145	UADD16	Unsigned halfword-wise Add	UADD16{cond} {Rd,} Rn, Rm
A.1.146	UASX	Unsigned Add Subtract Exchange	UASX{cond} {Rd,} Rn, Rm
A.1.147	UBFX	Unsigned Bit Field Extract	UBFX{cond} Rd, Rn, #lsb, #width
A.1.148	UDIV	Unsigned Divide	UDIV{cond}{q} {Rd,} Rn, Rm
A.1.149	UHADD8	Unigned Halving bytewise Add	UHADD8{cond} {Rd,} Rn, Rm
A.1.150	UHADD16	Unsigned Halving halfword-wise Add	UHADD16{cond} {Rd,} Rn, Rm
A.1.151	UHASX	Unsigned Halving Add Subtract Exchange	UHASX{cond} {Rd,} Rn, Rm
A.1.152	UHSAX	Unsigned Halving Subtract Add Exchange	UHSAX{cond} {Rd}, Rn, Rm
A.1.153	UHSUB8	Unsigned Halving bytewise Subtraction	UHSUB8{cond} {Rd,} Rn, Rm
A.1.154	UHSUB16	Unsigned Halving halfword-wise Subtract	UHSUB16{cond} {Rd}, Rn, Rm
A.1.155	UMAAL	Unsigned Multiply Accumulate Long; 64 <= 32 + 32 + 32 x 32	UMAAL{cond} RdLo, RdHi, Rn, Rm
A.1.156	UMLAL	Unsigned Multiply Accumulate 64 <= 64 + 32 x 32	UMLAL{S}{cond} RdLo, RdHi, Rn, Rm
A.1.157	UMULL	Unsigned Multiply; 64 <= 32 x 32	UMULL{S}{cond} RdLo, RdHi, Rn, Rm
A.1.158	UQADD8	Saturating Unsigned bytewise Add	UQADD8{cond} {Rd,} Rn, Rm
A.1.159	UQADD16	Saturating Unsigned halfword-wise Add	UQADD16{cond} {Rd,} Rn, Rm
A.1.160	UQASX	Saturating Unsigned Add Subtract Exchange	UQASX{cond} {Rd,} Rn, Rm
A.1.161	UQSAX	Saturating Unsigned Subtract Add Exchange	UQSAX{cond} {Rd,} Rn, Rm
A.1.162	UQSUB8	Saturating Unsigned bytewise Subtract	UQSUB8{cond} {Rd,} Rn, Rm
A.1.163	UQSUB16	Saturating Unsigned halfword Subtract	UQSUB16{cond} {Rd,} Rn, Rm
A.1.164	USAD8	Unsigned Sum of Absolute Differences	USAD8{cond} Rd, Rn, Rm
A.1.165	USADA8	Unsigned Sum of Absolute Differences Accumulate	USADA8{cond} Rd, Rn, Rm, Ra
A.1.166	USAT	Unsigned Saturate	USAT{cond} Rd, #sat, Rm{, shift}
A.1.167	USAT16	Unigned Saturate, parallel halfwords	USAT16{cond} Rd, #sat, Rn
A.1.168	USAX	Unsigned Subtract Add Exchange	USAX{cond} {Rd,} Rn, Rm
A.1.169	USUB8	Unsigned bytewise Subtraction	USUB8{cond} {Rd,} Rn, Rm
A.1.170	USUB16	Unsigned halfword-wise Subtract	USUB16{cond} {Rd,} Rn, Rm
A.1.171	UXT	Unsigned Extend	UXT<extend>{cond} {Rd,} Rm {,rotation}
A.1.172	UXTA	Unsigned Extend and Add	UXTA<extend>{cond} {Rd,} Rn, Rm {,rotation}
A.1.173	WFE	Wait for Event	WFE{cond}
A.1.174	WFI	Wait For Interrupt	WFI{cond}
A.1.175	YIELD	YIELD	YIELD{cond}

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ARM DEN0013C - Appendix A Instruction Summary